OMAP3530_08 Datasheet, PDF (205/264 Pages) Texas Instruments – Applications Processor

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OMAP3530/25 Applications Processor
SPRS507B – FEBRUARY 2008 – REVISED JULY 2008
Table 6-48. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Receive Mode⁽¹⁾
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX MIN MAX
B3
t_{su(DRV-CLKXAE)}
Setup time, mcbspx_dr valid before
Master
5.6
12
ns
mcbspx_clkx active edge
Slave
5.8
12.2
ns
B4
t_{h(CLKXAE-DRV)}
Hold time, mcbspx_dr valid after mcbspx_clkx Master
1
1
ns
active edge
Slave
0.4
0.4
ns
B5 t_{su(FSXV-CLKXAE)} Setup time, mcbspx_fsx valid before mcbspx_clkx active edge
5.8
12.2
ns
B6
t_{h(CLKXAE-FSXV)}
Hold time, mcbspx_fsx valid after mcbspx_clkx active edge
0.5
0.5
ns
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in Table 6-46 and Table 6-47.
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
Table 6-49. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Receive
Mode ⁽¹⁾
NO.
PARAMETER
B2
t_{d(CLKXAE-FSXV)}
Delay time, mcbspx_clkx active edge to mcbspx_fsx valid
1.15 V
MIN MAX
0.7
22.2
1.0 V
MIN MAX
0.7 44.4
UNIT
ns
mcbspx_clkr
mcbspx_fsr
mcbspx_dr
B2
B2
B3
B4
D7
D6
Figure 6-33. McBSP Rising Edge Receive Timing in Master Mode
D5
030-068
mcbspx_clkr
mcbspx_fsr
mcbspx_dr
B5
B6
B3
B4
D7
D6
D5
030-069
Figure 6-34. McBSP Rising Edge Receive Timing in Slave Mode
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in Table 6-46 and Table 6-47.
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
6.6.1.1.2 Transmit Timing with Rising Edge as Activation Edge
Table 6-50 through Table 6-55 assume testing over the recommended operating conditions (see
Figure 6-35 and Figure 6-36).
Table 6-50. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Transmit Mode⁽¹⁾
NO.
PARAMETER
B5 t_{su(FSXV-CLKXAE)} Setup time, mcbspx_fsx valid before mcbspx_clkx
active edge
1.15 V
MIN
MAX
3.7
1.0 V
MIN
MAX
7.9
UNIT
ns
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 205