OMAP3530_08 Datasheet, PDF (142/264 Pages) Texas Instruments – Applications Processor

OMAP3530/25 Applications Processor
SPRS507B – FEBRUARY 2008 – REVISED JULY 2008
www.ti.com
4.3 DPLL and DLL Specifications
The OMAP3530/25 integrates six DPLLs and a DLL. The PRM and CM drive five of them, while the sixth
(not supported) is controlled by the display controller.
The five main DPLLs are:
• DPLL1 (MPU)
• DPLL2 (IVA2)
• DPLL3 (Core)
• DPLL4 (Peripherals)
• DPLL5 (Second Peripherals DPLL)
Figure 4-9 illustrates the DLL and DPLL implementation.
vdds_dpll_dll
OMAP
Power Rail
DPLL1
DPLL2
DLL
DPLL3
DPLL4
DPLL5
vdds_dpll_per
(1) Figure 4-9. DPLL and DLL Implementation
030-016
For more information on the OMAP3530/25 Applications Processor DPLLs and clocking structure, see the
Power, Reset, and Clock management (PRCM) chapter of the OMAP35x Applications Processor TRM
(literature number SPRUFA5).
4.3.1 Digital Phase-Locked Loop (DPLL)
The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the
OMAP3530/25 device.
DPLL1 and DPLL2 get an always-on clock used to produce the synthesized clock. They get a high-speed
bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode.
The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor
power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes
performance during frequency scaling.
Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,
all DPLL outputs can be controlled by an independent divider (M2 to M6).
The clock generating DPLLs of the OMAP3530/25 device have following features:
• Independent power domain per DPLL
• Controlled by clock-manager (CM)
• Fed with always-on system clock with independent gating control per DPLL
142 CLOCK SPECIFICATIONS
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