OMAP3515 Datasheet, PDF (204/227 Pages) Texas Instruments – Applications Processor

OMAP3515/03 Applications Processor
SPRS505 – FEBRUARY 2008
www.ti.com
Table 6-112. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode^(1)(2)(3)(4) (continued)
NO.
PARAMETER
MMC3 t_{su(CMDV-CLKIH)}
Setup time, mmc1_cmd valid before mmc1_clk
rising clock edge
MMC4 t_{su(CLKIH-CMDIV)}
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
MMC7 t_{su(DATxV-CLKIH)}
Setup time, mmc1_datx valid before mmc1_clk
rising clock edge
MMC8 t_{su(CLKIH-DATxIV)}
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
MMC/SD/SDIO Interface 2
MMC3 t_{su(CMDV-CLKIH)}
Setup time, mmc2_cmd valid before mmc2_clk
rising clock edge
MMC4 t_{su(CLKIH-CMDIV)}
Hold time, mmc2_cmd valid after mmc2_clk
rising clock edge
MMC7 t_{su(DATxV-CLKIH)}
Setup time, mmc2_datx valid before mmc2_clk
rising clock edge
MMC8 t_{su(CLKIH-DATxIV)}
Hold time, mmc2_datx valid after mmc2_clk
rising clock edge
MMC/SD/SDIO Interface 3
MMC3 t_{su(CMDV-CLKIH)}
Setup time, mmc3_cmd valid before mmc3_clk
rising clock edge
MMC4 t_{su(CLKIH-CMDIV)}
Hold time, mmc3_cmd valid after mmc3_clk
rising clock edge
MMC7 t_{su(DATxV-CLKIH)}
Setup time, mmc3_datx valid before mmc3_clk
rising clock edge
MMC8 t_{su(CLKIH-DATxIV)}
Hold time, mmc3_datx valid after mmc3_clk
rising clock edge
1.15 V
MIN
MAX
5.6
2.3
5.6
2.3
5.6
2.3
5.6
2.3
5.6
2.3
5.6
2.3
1.0 V
MIN
MAX
26
1.9
26
1.9
UNIT
ns
ns
ns
ns
26
ns
1.9
ns
26
ns
1.9
ns
26
ns
1.9
ns
26
ns
1.9
ns
(1) Timing parameters are referred to output clock specified in Table 6-113.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-113.
(3) Corresponding figures showing timing parameters are common with Standard MMC mode (See Figure 6-57 and Figure 6-58)
(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-113. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode⁽⁴⁾⁽⁷⁾
N O.
PARAMETER
High-Speed MMC Mode
MMC1 t_c(clk)
Cycle time⁽¹⁾, output clk period
MMC2 t_W(clkH)
Typical pulse duration, output clk high
MMC2 t_W(clkL)
Typical pulse duration, output clk low
t_dc(clk)
t_j(clk)
Duty cycle error, output clk
Jitter standard deviation⁽³⁾, output clk
MMC/SD/SDIO Interface 1 (1.8 V IO)
MMC5
t_c(clk)
t_W(clkH)
t_W(clkL)
t_dc(clk)
t_d(CLKOH-CMD)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
MMC6 t_{d(CLKOH-DATx)} Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
MMC/SD/SDIO Interface 1 (3.0 V IO)
1.15 V
MIN
MAX
1.0 V
MIN
MAX
20.8
X⁽⁵⁾*PO⁽²⁾
Y⁽⁶⁾*PO⁽²⁾
1041.7
200
41.7
X⁽⁵⁾*PO⁽²⁾
Y⁽⁶⁾*PO⁽²⁾
2083.3
200
3
3
3
3
3
3
3
3
3.7
14.1
4.1
34.5
3.7
14.1
4.1
34.5
UNIT
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
204 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
Submit Documentation Feedback