OMAP3515 Datasheet, PDF (190/227 Pages) Texas Instruments – Applications Processor

OMAP3515/03 Applications Processor
SPRS505 – FEBRUARY 2008
HSU0
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hsusb0_clk
hsusb0_stp
hsusb0_dir_&_nxt
hsusb0_data[7:0]
HSU1
HSU1
HSU3
HSU4
HSU2
Data_OUT
HSU2
HSU5
Data_IN
HSU6
Figure 6-43. High-Speed USB – 12-bit Slave Mode
030-086
6.6.4.2 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 – 12-bit Master Mode
Table 6-90 and Table 6-91 assume testing over the recommended operating conditions (see Figure 6-44).
Input Conditions
t_R
t_F
Output Conditions
C_LOAD
Table 6-89. High-Speed USB Timing Conditions – 12-bit Master Mode
TIMING CONDITION PARAMETER
VALUE
Input signal rise time
2
Input signal fall time
2
Output load capacitance
3
UNIT
ns
ns
pF
Table 6-90. High-Speed USB Timing Requirements – 12-bit Master Mode⁽¹⁾
NO.
PARAMETER
HSU3
HSU4
HSU5
HSU6
t_s(DIRV-CLKH)
t_s(NXTV-CLKH)
t_{h(CLKH-DIRIV)}
t_{h(CLKH-NXT/IV)}
t_{s(DATAV-CLKH)}
t_{h(CLKH-DATIV)}
Setup time, hsusbx_dir valid before hsusbx_clk rising edge
Setup time, hsusbx_nxt valid before hsusbx_clk rising edge
Hold time, hsusbx_dir valid after hsusbx_clk rising edge
Hold time, hsusbx_nxt valid after hsusbx_clk rising edge
Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge
Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge
(1) In hsusbx, x is equal to 1 or 2.
1.15 V
MIN
MAX
9.3
9.3
0.2
0.2
9.3
0.2
UNIT
ns
ns
ns
ns
ns
ns
Table 6-91. High-Speed USB Switching Characteristics – 12-bit Master Mode⁽¹⁾
N O.
PARAMETER
HSU0
HSU1
HSU2
f_p(CLK)
t_j(CLK)
t_d(clkL-STPV)
t_{d(clkL-STPIV)}
t_d(clkL-DV)
t_d(clkL-DIV)
t_R(do)
t_F(do)
hsusbx_clk clock frequency
Jitter standard deviation⁽²⁾, hsusbx_clk
Delay time, hsusbx_clk high to output hsusbx_stp valid
Delay time, hsusbx_clk high to output hsusbx_stp invalid
Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid
Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid
Rise time, output signals
Fall time, output signals
(1) In hsusbx, x is equal to 1 or 2.
1.15 V
MIN
MAX
60
200
13
2
13
2
2
2
UNIT
MHz
ps
ns
ns
ns
ns
ns
ns
190 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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