OMAP3515 Datasheet, PDF (154/227 Pages) Texas Instruments – Applications Processor

OMAP3515/03 Applications Processor
SPRS505 – FEBRUARY 2008
cam_xclki
ISP16
ISP15
ISP16
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cam_pclk
ISP17
ISP18
ISP18
cam_vs
ISP19
ISP20
cam_hs
ISP21
ISP22
cam_d[11:0]
ISP23
D(0) D(n-3) D(n-2) D(n-1)
ISP24
D(0) D(1)
D(n-1)
cam_wen
ISP25
ISP26
cam_fld
030-056
Figure 6-17. ISP – 12-Bit SYNC Normal – Progressive Mode^{(1)(2)(3)(4)(5)(6)(7)(8)}
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the
signal length can be set.
(2) The parallel camera in SYNC mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data.
(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be
grounded.
(4) However, it is possible to shift the data to 0, 2, or 4 data internal lanes.
(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit
mode, and cam_d[11:0] in 12-bit mode.
(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.
(7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and
cam_wen signals are asserted.
(8) In cam_xclki; I is equal to a or b.
6.5.1.1.1.2 8-bit Packed SYNC – Progressive Mode
Table 6-17 and Table 6-18 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-18).
Table 6-16. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
Input signal rise time
Input signal fall time
VALUE
2.5
2.5
UNIT
ns
ns
154 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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