OMAP3515 Datasheet, PDF (139/227 Pages) Texas Instruments – Applications Processor

www.ti.com
OMAP3515/03 Applications Processor
SPRS505 – FEBRUARY 2008
Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters⁽¹⁾⁽²⁾ (continued)
NO.
PARAMETER
1.15 V
MIN
MAX
FI5 Maximum address valid generation delay from internal
6.5
functional clock
FI6 Maximum byte enable generation delay from internal
6.5
functional clock
FI7 Maximum output enable generation delay from internal
6.5
functional clock
FI8 Maximum write enable generation delay from internal
6.5
functional clock
FI9 Maximum functional clock skew
100
1.0 V
MIN
MAX
9.1
9.1
9.1
9.1
170
0.9 V
MIN
MAX
13.7
13.7
13.7
13.7
200
UNIT
ns
ns
ns
ns
ps
(1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field. Internal
parameters are referred to the GPMC functional internal clock which is not provided externally.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode
NO.
PARAMETER
FA5⁽¹⁾
FA20⁽³⁾
FA21⁽²⁾
t_acc(DAT)
Data maximum access
time
t_{acc1-pgmode(DAT)} Page mode successive
data maximum access
time
t_{acc2-pgmode(DAT)} Page mode first data
maximum access time
1.15 V
MIN
MAX
H⁽⁵⁾
P⁽⁴⁾
1.0 V
MIN
MAX
H⁽⁵⁾
P⁽⁴⁾
0.9 V
MIN
MAX
H⁽⁵⁾
P⁽⁴⁾
UNIT
GPMC_FCLK cycles
GPMC_FCLK cycles
H⁽⁵⁾
H⁽⁵⁾
H⁽⁵⁾ GPMC_FCLK cycles
(1) The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(3) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of
GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1)
(5) H = AccessTime * (TimeParaGranularity + 1)
Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
MIN
MAX
MIN
MAX
MIN
MAX
t_R(DO)
Rise time, output data
2.0
2.0
2.0
FA0
t_F(DO)
t_W(nBEV)
Fall time, output data
Pulse duration,
gpmc_nbe0_cl
e, gpmc_nbe1
valid time
Read
Write
2.0
N⁽¹²⁾
N⁽¹²⁾
2.0
N⁽¹²⁾
N⁽¹²⁾
2.0
N⁽¹²⁾
N⁽¹²⁾
FA1 t_W(nCSV)
Pulse duration, Read
A⁽¹⁾
A⁽¹⁾
A⁽¹⁾
gpmc_ncsx⁽¹³⁾
v low
Write
A⁽¹⁾
A⁽¹⁾
A⁽¹⁾
FA3
t_{d(nCSV-nADVIV)}
Delay time,
Read
gpmc_ncsx⁽¹³⁾
valid to
Write
B⁽²⁾ – 0.2
B⁽²⁾ – 0.2
B⁽²⁾ + 2.0
B⁽²⁾ + 2.0
B⁽²⁾ – 0.2
B⁽²⁾ – 0.2
B⁽²⁾ + 2.6
B⁽²⁾ + 2.6
B⁽²⁾ – 0.2
B⁽²⁾ – 0.2
B⁽²⁾ + 3.7
B⁽²⁾ + 3.7
gpmc_nadv_al
e invalid
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Submit Documentation Feedback
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 139