LMH6523_15 Datasheet, PDF (20/33 Pages) Texas Instruments – High Performance Quad DVGA

LMH6523
SNOSC88 – DECEMBER 2012
Table 3. Pins with Dual Functions
PIN
MODE = 0
45
A4
46
A3
47
A2
48
A1
MODE = 1
SDO ⁽¹⁾
SDI
CSb
CLK
(1) Pin 45 requires external bias. See Serial Mode Section for Details.
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PARALLEL INTERFACE
Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space
dedicated to control lines. When designing a system that requires very fast gain changes parallel mode is the
best selection. To place the LMH6523 into parallel mode the MODE pin (pin 5) is set to the logical zero state.
Alternately the MODE pin can be connected directly to ground.
The attenuator control pins are internally biased to logic high state with weak pull up resistors. The MODE pin
has a weak internal resistor to ground.
The LMH6523 has a 5-bit gain control bus. Data from the gain control pins is immediately sent to the gain circuit
(i.e., gain is changed immediately). To minimize gain change glitches all gain pins should change at the same
time. In order to achieve the very fast gain step switching time the internal gain change circuit is very fast. Gain
glitches could result from timing skew between the gain set bits. This is especially the case when a small gain
change requires a change in state of three or more gain control pins. If necessary the DVGA could be put into a
disabled state while the gain pins are reconfigured and then brought active when they have settled.
ENA , ENB, ENC and END pins are provided to reduce power consumption by disabling the highest power
portions of the LMH6523. The gain register will preserve the last active gain setting during the disabled state.
These pins have three logic states and will float to the middle or low power, enabled state if left floating. When
grounded the EN pins will disable the associated channel and when biased to the highest logic level the
associated channel will be in the high power, enabled state. See the Typical Performance section for disable and
enable timing information.
CONTROL LOGIC
pd
ga[4:0]
gb[4:0]
gc[4:0]
gd[4:0]
LMH6523
4
en[a:d]*
5
ga[4:0]
5
gb[4:0]
5
gc[4:0]
5
gd[4:0]
*Enable pins are tri state buffer compatible.
SVA-30206517
Figure 51. Parallel Mode Connection
SPI COMPATIBLE SERIAL INTERFACE
Serial interface allows a great deal of flexibility in gain programming and reduced board complexity. Using only 4
wires for both channels allows for significant board space savings. The trade off for this reduced board
complexity is slower response time in gain state changes. For systems where gain is changed only infrequently
or where only slow gain changes are required serial mode is the best choice. To place the LMH6523 into serial
mode the MODE pin (Pin 5) should be put into the logic high state. Alternatively the MODE pin an be connected
directly to the 5V supply bus.
The LMH6523 serial interface is a generic 4-wire synchronous interface that is compatible with SPI type
interfaces that are used on many microcontrollers and DSP controllers. The serial mode is active when the mode
pin is set to a logic 1 state. In this configuration the pins function as shown in the pin description table. The SPI
interface uses the following signals: clock input (CLK), serial data in (SDI), serial data out, and serial chip select
(CSb). The chip select pin is active low.
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