TLK2501 Datasheet, PDF (15/25 Pages) Texas Instruments – 1.5 TO 2.5 GBPS TRANSCEIVER

TLK2501
1.5 TO 2.5 GBPS TRANSCEIVER
SLLS427D − AUGUST 2000 − REVISED JULY 2003
reference clock (GTX_CLK) timing requirements over recommended operating conditions (unless
otherwise noted)
PARAMETER
Frequency
Frequency
Frequency tolerance
Duty cycle
Jitter
TEST CONDITIONS
Minimum data rate
Maximum data rate
Peak-to-peak
MIN
Typ −0.01%
Typ −0.01%
− 100
40%
TYP MAX
75 Typ+0.01%
125 Typ+0.01%
50%
60%
40
UNIT
MHz
MHz
ppm
%
ps
TTL input electrical characteristics over recommended operating conditions (unless otherwise
noted), TTL signals: TXDO−TXD15, GTX_CLK, LOOPEN, LCKREFN, PRBSEN
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
Input high current
IIL
Input low current
CI
Input capacitance
tr
Rise time, GTX_CLK, TX_EN, TX_ER, TXD
tf
Fall time, GTX_CLK, TX_EN, TX_ER, TXD
tsu
TXD, TX_EN, TX_ER setup to ↑ GTX_CLK
th
TXD, TX_EN, TX_ER hold to ↑ GTX_CLK
TEST CONDITIONS
See Figure 10
See Figure 10
VDD = MAX, VIN = 2 V
VDD = MAX, VIN = 0.4 V
0.8 V to 2 V
0.8 V to 2 V, C = 5 pF,
See Figure 10
2 V to 0.8 V, C = 5 pF,
See Figure 10
See Figure 10
See Figure 10
MIN NOM
1.7
− 40
1
MAX
3.6
0.80
40
4
UNIT
V
V
µA
µA
pF
ns
1
ns
1.5
ns
0.4
ns
GTX_CLK
TX_ER, TX_EN,
TXD(0−15)
tr
tf
tsu
tr
tf
th
Figure 10. TTL Data Input Valid Levels for AC Measurements
3.6 V
2.0 V
0.8 V
0V
3.6 V
2.0 V
0.8 V
0V
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