TLK2501 Datasheet, PDF (12/25 Pages) Texas Instruments – 1.5 TO 2.5 GBPS TRANSCEIVER

TLK2501
1.5 TO 2.5 GBPS TRANSCEIVER
SLLS427D − AUGUST 2000 − REVISED JULY 2003
synchronization and initialization (continued)
If during normal transmission and reception, an invalid code is received, the TLK2501 notifies the attached
system or protocol device as described in comma detect and 8-bit/10-bit decoding. The synchronization state
machine transitions to the CHECK state. The CHECK state determines whether the invalid code received was
caused by a spurious event or a loss of the link. If, in the CHECK state, the decoder sees 4 consecutive valid
codes, the state machine determines the link is good and transitions back to the SYNC state for normal
operation. If, in the CHECK state, the decoder sees 3 invalid codes (not required to be consecutive), the
TLK2501 determines a loss of the link has occurred and transition the synchronization-state machine back to
the link-acquisition state (ACQ).
The state of the transmit data bus, control terminals, and serial outputs during the link acquisition process is
illustrated in Figure 7.
ACQ
SYNC
TX_EN ^{xx xx xx xx xx xx xx}
TX_ER xx xx xx xx xx xx xx
TXD(0−15) xx xx xx xx xx xx xx xx
DOUTTXP,
DOUTTXN
IDLE
D0−D15
D0−D15
Ca. Ext.
Error
Figure 7. Transmit Side Timing Diagram
The state of the receive data bus, status terminals, and serial inputs during the link acquisition process is
illustrated in Figure 8 and Figure 9.
ACQ
SYNC
DINRXP,
DINRXN
IDLE or Carrier
Extend
IDLE or Carrier
Extend
IDLE or Carrier
Extend
D0−D15
RXD(0−15)
XXXXXXXXXXXXXXXXXXX
IDLE or Carrier
Extend
IDLE or Carrier
Extend
D0−D15
RX_ER
RX_DV,
RESET
(Internal Signal)
Figure 8. Receive Side Timing Diagram (Idle or Carrier Extend)
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