LP2996LQ Datasheet, PDF (14/26 Pages) Texas Instruments – LP2996-N DDR Termination Regulator

LP2996-N
SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013
VDDQ
VDD
+
CIN
LP2996
VDDQ
AVIN
VTT
PVIN
VSENSE
GND
VTT
R1
+
COUT
R2
www.ti.com
Figure 29. Increasing VTT by Level Shifting
Conversely, the R2 resistor can be placed between V_SENSE and V_DDQ to shift the V_TT output lower than the
internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below:
V_TT = VDDQ/2 (1 - R1/R2)
(12)
VDDQ
VDD
+
CIN
LP2996
VDDQ
VSENSE
AVIN
PVIN
VTT
GND
R2
R1
VTT
+
COUT
Figure 30. Decreasing VTT by Level Shifting
HSTL APPLICATIONS
The LP2996-N can be easily adapted for HSTL applications by connecting V_DDQ to the 1.5V rail. This will
produce a V_TT and V_REF voltage of approximately 0.75V for the termination resistors. AVIN and PVIN should be
connected to a 2.5V rail for optimal performance.
SD
VDDQ = 1.5V
VDD = 2.5V
+
CIN
LP2996
SD
VDDQ
VREF
AVIN
VSENSE
PVIN
VTT
GND
+
CREF
VREF = 0.75V
+
COUT
VTT = 0.75V
Figure 31. HSTL Application
QDR APPLICATIONS
Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this
increase in bus lines has the effect of increasing the current levels required for termination. The recommended
approach in terminating multiple channels is to use a dedicated LP2996-N for each channel. This simplifies
layout and reduces the internal power dissipation for each regulator. Separate V_REF signals can be used for each
DIMM bank from the corresponding regulator with the chipset reference provided by a local resistor divider or
one of the LP2996-N signals. Because V_REF and V_TT are expected to track and the part to part variations are
minor, there should be little difference between the reference signals of each LP2996-N.
14
Submit Documentation Feedback
Product Folder Links: LP2996-N
Copyright © 2002–2013, Texas Instruments Incorporated