LP2996LQ Datasheet, PDF (12/26 Pages) Texas Instruments – LP2996-N DDR Termination Regulator

LP2996-N
SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013
SD
VDDQ = 2.5V
VDD = 2.5V
+
CIN
LP2996
SD
VDDQ
AVIN
VREF
VSENSE
PVIN
VTT
GND
+
CREF
VREF = 1.25V
+
COUT
VTT = 1.25V
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Figure 24. Recommended SSTL-2 Implementation
If power dissipation or efficiency is a major concern then the LP2996-N has the ability to operate on split power
rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog circuitry (AVIN) can
be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered
when sourcing current from V_TT. The disadvantage of this circuit is that the maximum continuous current is
reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications.
Increasing the output capacitance can also help if periods of large load transients will be encountered.
SD
VDDQ = 2.5V
AVIN = 2.2V to 5.5V
PVIN = 1.8V
+
CIN
LP2996
SD
VDDQ
VREF
AVIN
VSENSE
PVIN
VTT
GND
+
CREF
VREF = 1.25V
+
COUT
VTT = 1.25V
Figure 25. Lower Power Dissipation SSTL-2 Implementation
The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not desirable to
use 2.5V, is to connect the LP2996-N power rail to 3.3V. In this situation AVIN will be limited to operation on the
3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum
continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the
LP2996-N from experiencing large current levels which cause the junction temperature to exceed the maximum.
Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V
rail.
SD
VDDQ = 2.5V
AVIN = 3.3V or 5V
PVIN = 3.3V
+
CIN
LP2996
SD
VDDQ
VREF
AVIN
VSENSE
PVIN
VTT
GND
+
CREF
VREF = 1.25V
+
COUT
VTT = 1.25V
Figure 26. SSTL-2 Implementation with higher voltage rails
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