LP2996LQ Datasheet, PDF (10/26 Pages) Texas Instruments – LP2996-N DDR Termination Regulator

LP2996-N
SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013
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90
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0
SOP Board
JEDEC Board
200 400 600 800 1000
AIRFLOW (Linear Feet per Minute)
Figure 21. θ_JA vs Airflow (SOIC-8)
Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an
internal ground plane. Using larger traces and more copper on the top side of the board can also help. With
careful layout it is possible to reduce the θ_JA further than the nominal values shown in Figure 21
Layout is also extremely critical to maximize the output current with the WQFN package. By simply placing vias
under the DAP the θ_JA can be lowered significantly. Figure 22 shows the WQFN thermal data when placed on a
4-layer JEDEC board with copper thickness of 0.5/1/1/0.5 oz. The number of vias, with a pitch of 1.27 mm, has
been increased to the maximum of 4 where a θ_JA of 50.41°C/W can be obtained. Via wall thickness for this
calculation is 0.036 mm for 1oz. Copper.
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0
1
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4
NUMBER OF VIAS
Figure 22. WQFN-16 θ_JA vs # of Vias (4 Layer JEDEC Board))
Additional improvements in lowering the θ_JA can also be achieved with a constant airflow across the package.
Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 23 shows how the θ_JA varies
with airflow.
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