GTL2010 Datasheet, PDF (14/15 Pages) NXP Semiconductors – 10-bit GTL Processor Voltage Clamp

PW (R-PDSO-G**)
14 PINS SHOWN
0,65
14
0,30
0,19
8
0,10 M
4,50 6,60
4,30 6,20
1
7
A
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PLASTIC SMALL-OUTLINE PACKAGE
0,15 NOM
Gage Plane
0°– 8°
0,25
0,75
0,50
1,20 MAX
0,15
0,05
Seating Plane
0,10
PINS **
8
DIM
14
16
20
24
28
A MAX
3,10 5,10 5,10 6,60 7,90 9,80
A MIN
2,90 4,90 4,90 6,40 7,70 9,60
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
4040064/F 01/97
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265