TLC6C5712-Q1_15 Datasheet, PDF (13/64 Pages) Texas Instruments – TLC6C5712-Q1 12-Channel, Full-Diagnostic, Constant-Current-Sink LED Driver With 8-Bit Dot Correction

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TLC6C5712-Q1
SLVSCO9A – AUGUST 2015 – REVISED AUGUST 2015
Feature Description (continued)
7.3.2.1 Recovery From Error
When any fault occurs, all FAULT information can be read in separate FAULT registers, for example,
<READ_OPEN_FAULT0>. When the error condition recovers, the register information is still latched and the
ERR pin remains low until the fault is masked or the RESET_STATUS command has been issued. However, if
the error condition still exists after issuing the RESET_STATUS command, the ERR pin pulls low again and the
corresponding FAULT register is set HIGH.
7.3.2.2 RESET_STATUS Command
The RESET_STATUS command clears all flags in the following registers:
<READ_ADJSHORT0>
<READ_ADJSHORT1>
<READ_SHORT_FAULT0>
<READ_SHORT_FAULT1>
<READ_SHORT_GND_FAULT0>
<READ_SHORT_GND_FAULT1>
<READ_OPEN_FAULT0>
<READ_OPEN_FAULT1>
<READ_PWM_FAULT>
<READ_STATUS0>, excluding the [POR_ERR_FLAG] bit.
As mentioned in the POR section, only the RESET_POR command can clear the [POR_ERR_FLAG] bit.
[POR_ERR_FLAG] bit: Read only (R) bit. HIGH: A POR error has occurred. To reset this flag, issue a
RESET_POR command.
[POR_MASK] bit: Read and write (R/W) bit. HIGH: A POR error is stored in the [POR_ERR_FLAG] bit
and is not reported to ERR.
RESET_POR: A command to reset [POR_ERR_FLAG].
SOFTWARE_POR: A command to generate a POR. It also clears STATUS flags.
See the following addresses in Table 2: 62h, 9Ah through A2h, A8h, and A9h.
7.3.3 PWM Input
The TLC6C5712-Q1 device has six PWM inputs with independently configurable mapping to modulate any of the
12 channels for external PWM dimming. A PWM monitor can be used to supervise PWM input-signal integrity.
7.3.3.1 PWM Dimming
PWM dimming is supported on all 12 channels by six PWM inputs. The input PWMx signal is active-low. Due to
the minimal pulse duration needed for diagnostics, at 200 Hz the minimum achievable duty cycle is 0.1%, or 5 µs
minimal on-time. Similarly, the maximum achievable duty cycle is 99.2%, or 40 µs minimum off-time. The setting
of this boundary allows enough time for diagnostic functions. In the case of 0% or 100% PWM, diagnostics are
not reported.
7.3.3.2 PWM Monitor
Independent rising-edge triggered timers are implemented as PWM monitors for each PWMx input channel.
when the timer length reaches the threshold t_PWM, [PWM_FAULTx] is set to HIGH. If the corresponding masking
register [PWM_FAULT_MASKx] is also set HIGH, the fault is stored in [PWM_FAULTx] and is not reported to the
[ANY_PWM_FAULT_FLAG] register. [ANY_PWM_FAULT_FLAG] is set to HIGH and the ERR pin is pulled LOW
if any of the PWM monitors reported a fault and the mask register [PWM_MASK] is disabled. The PWM rising
edge resets the timer and restarts counting from 0. For 0% or 100% PWM, the [PWM_FAULTx] registers should
be independently masked for each PWMx input via the [PWM_FAULT_MASKx] registers.
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