THS6032 Datasheet, PDF (13/31 Pages) Texas Instruments – LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER
SLOS233C – APRIL1999 – REVISED MARCH 2000
APPLICATION INFORMATION
ADSL (continued)
The ADSL transmit band consists of 255 separate carrier frequencies, each with its own modulation and
amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as
low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier
frequencies or it creates intermodulation products that interfere with ADSL carrier frequencies.
The THS6032 has been specifically designed for ultralow distortion by careful circuit implementation and by
taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended
distortion measurements are shown in Figures 11 – 15. It is commonly known that in the differential driver
configuration, the second order harmonics tend to cancel out. Thus, the dominant total harmonic distortion
(THD) will be primarily due to the third order harmonics. Additionally, distortion should be reduced as the
feedback resistance drops. This is because the bandwidth of the amplifier increases, which allows the amplifier
to react faster to any nonlinearities in the closed-loop system.
Another significant point is the fact that distortion decreases as the impedance load increases. This is because
the output resistance of the amplifier becomes less significant as compared to the output load resistance.
One problem that has been receiving a lot of attention in the ADSL area is power dissipation. One way to
substantially reduce power dissipation is to lower the power supply voltages. This is because the RMS voltage
of an ADSL central office signal is 1.65-V RMS at each driver’s output with a 1:2 transformer. But, to meet ADSL
requirements, the drivers must have a voltage peak-to-RMS crest factor of 5.6 in order to keep the bit-error
probability rate below 10^{– 7}. Hence, the power supply voltages must be high enough to accomplish the driver’s
peak output voltage of 1.65 V × 5.6 = 9.25 V_{(PEAK )}.
This high peak output voltage requirement, coupled with a low RMS voltage requirement, does not lend itself
to conventional high efficiency designs. One way to save power is to decrease the bias currents internal to the
amplifier. The drawback of doing this is an increase in distortion and a lower frequency response bandwidth.
This is where the THS6032 class-G architecture is useful. The class-G output stage utilizes both a high supply
voltage [V_CC(H) typically ± 15 V] and a low supply voltage [(V_CC(L) typically ± 6 V]. As long as the output voltage
is less than [V_CC(L) – 2.5 V], then part of the output current will be drawn from the V_CC(L) supplies. If the output
signal goes above this cutoff point [for example, V_O > V_CC(L) – 2.5 V], then all of the output current will be supplied
by V_CC(H).
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