THCV226_16 Datasheet, PDF (9/27 Pages) THine Electronics, Inc. – THCV226 is designed to support video data transmission between the host and display.

Multiple-chip Configuration
In order to reduce the number of cables needed for HTPDN and LOCKN in multiple-chip configuration,
THCV226 is equipped with the DGLOCK pin. When all the DGLOCK pins are connected as in Figure 6 ,
the connected Rx chips can share the CDR lock status via DGLOCK, making all the Rx chips in the same
operation status.
Transmitter
(Tx side)
HTPDN
(Tx side)
LOCKN
VDD
PDN
HTPDN
(Rx side)
LOCKN
THCV226
Transmitter
HTPDN
LOCKN
Transmitter
HTPDN
DGLOCK
PDN
HTPDN
THCV226
LOCKN
Transmitter
HTPDN
LOCKN
LOCKN
DGLOCK
Figure 6. Usage of DGLOCK in Multiple-Rx Configuration
Field BET Operation
In order to help to debug high-speed serial links of CML lines, THCV226 has an operation mode acted as the
bit error tester (Field BET). In the Field BET mode, the on-chip pattern generator on V-by-One^® HS transmitter
side is enabled and generates a test pattern. THCV217, which is an example of Tx device, has this function mode.
In this mode, THCV217 internally generates the test pattern, encodes the data according to the 8b10b protocol,
scrambles, and then serializes onto the CML high-speed lines.
THCV226 receives the data stream and checks whether the sampled data has bit error.
“Field BET” mode of THCV226 is activated by setting BET_EN=1.
As for THCV226, when the internal test pattern check circuit is enabled, the pattern check result can be
monitored at the BETOUT pin. The BETOUT pin goes Low whenever bit errors occur and stays High when
there is no bit error. Please refer to Figure 7 and Figure 8.
Table 5 shows possible combination of Tx and Rx for normal and Field BET operation.
BETOUT
L
H
Result
Bit error occurred
No error
Table 4. Field BET Result
THCV226_Rev.1.10_E
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