THCV226_16 Datasheet, PDF (11/27 Pages) THine Electronics, Inc. – THCV226 is designed to support video data transmission between the host and display.

LVDS Output Enable Function
By setting the OE and OPF pins, the following output enable function can be selected.
In output disable condition, all the outputs take low fixed data or High-Z except for HTPDN, LOCKN and
DGLOCK.
LOCKN
H
L
OE
OPF
LVDS Outputs
Status
Output Condition
1
1
0
Output Enable
Low Fixed Data
Hi-Z
0
1
0
Output Disable
Low Fixed Data
Hi-Z
1
1
0
Output Enable
Normal Data
0
1
0
Output Disable
Low Fixed Data
Hi-Z
Table 7. LVDS Output Enable Function
LVDS Data Mapping
LVDS data (video data, control data, DE) are mapped as Figure 9. RLC[6] is special bit for DE (data enable).
RLC[5:4] are for control data bits, and the other bits are for video data. Also there are special assigned bits,
‘CTL’ transmitted under DE=0 condition.
The number of LVDS channels depends on color depth mode, COL.
RLD[6] is not available at COL=0, 8-bit color depth mode.
(RLCLKzp) – (RLCLKzn)
Vdiff = 0
tRCOP
Data width
32 24
Previous cycle
Current cycle
Next cycle
RLAzp/n
RLAz[1] RLAz[0] RLAz[6] RLAz[5] RLAz[4] RLAz[3] RLAz[2] RLAz[1] RLAz[0] RLAz[6] RLAz[5] RLAz[4] RLAz[3] RLAz[2] RLAz[1] RLAz[0]
RLBzp/n
RLBz[1] RLBz[0] RLBz[6] RLBz[5] RLBz[4] RLBz[3] RLBz[2] RLBz[1] RLBz[0] RLBz[6] RLBz[5] RLBz[4] RLBz[3] RLBz[2] RLBz[1] RLBz[0]
RLCzp/n
RLDzp/n
RLCz[1] RLCz[0] ^{RLCz[6] RLCz[5] RLCz[4]} RLCz[3] RLCz[2] RLCz[1] RLCz[0] ^{RLCz[6] RLCz[5] RLCz[4]} RLCz[3] RLCz[2] RLCz[1] RLCz[0]
(DE) (V)
(H)
(DE)
(V)
(H)
RLDz[1] RLDz[0] RLDz[6] RLDz[5] RLDz[4] RLDz[3] RLDz[2] RLDz[1] RLDz[0] RLDz[6] RLDz[5] RLDz[4] RLDz[3] RLDz[2] RLDz[1] RLDz[0]
RLEzp/n
z = 0,1,2,3
RLEz[1] RLEz[0] RLEz[6] RLEz[5] RLEz[4] RLEz[3] RLEz[2] RLEz[1] RLEz[0] RLEz[6] RLEz[5] RLEz[4] RLEz[3] RLEz[2] RLEz[1] RLEz[0]
Data Enable Control Data Bits
Figure 9. LVDS Output Switching Timing Diagram
THCV226_Rev.1.10_E
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11/27
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