THCV226_16 Datasheet, PDF (5/27 Pages) THine Electronics, Inc. – THCV226 is designed to support video data transmission between the host and display.

Functional Description
Functional Overview
With V-by-One^® HS’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
THCV226 enables the transmission of 8 or 10-bit video data, 2-bit synchronizing control data of HSYNC,
VSYNC, and Data Enable(DE), by a pair cable with minimal external components.
THCV226 automatically extracts the clock from the incoming data streams and converts the serial data into
video data with DE being high or synchronizing control data with DE being low, recognizing which type of
serial data is being sent by the transmitter. Also, THCV226 outputs the recovered data in the LVDS data format.
THCV226 can operate for a wide range of a serial bit rate from 1.2Gbps to 3.4Gbps. It is unnecessary to use
any external frequency reference, such as a crystal oscillator.
Data Enable Requirement (DE)
There are some requirements for DE signal as described in Figure1 and Figure2.
If DE=Low, control data of same cycle and particular assigned data bit ‘CTL’ except the first and last pixel are
transmitted. Otherwise video data is transmitted during DE=High.
Control data from source device in DE=High period is previous data of DE transition. See Figure2.
The length of DE being low and high must be at least 8 clock cycles long, as described in Figure17 and Table17.
DE must be toggled as High -> Low -> High at regular interval.
CTL Bit Transmission
There is particular assigned data bit ‘CTL’ which can be transmitted at blanking period except the first and the
last pixel on DE=Low.
Transmitter
Data bit : R/G/B, CONT
1
Control bit : HSYNC, VSYNC
Data bit : CTL*
0
THCV226
R/G/B
CONT
CTL
DE=1 , R/G/B, CONT
DE=0 , CTL* except the 1st and the last pixel
Other R/G/B, CONT=Low Fixed.
VSYNC
HSYNC
DE=1 , HSYNC, VSYNC=Fixed
DE=0 , HSYNC, VSYNC
DE
DE
CTL* are particular assigned bits among R/G/B, CONT that can carry arbitrary data during DE=Low period.
Figure 1. Conceptual Diagram of Basic Operation of Chipset
THCV226_Rev.1.10_E
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