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THC63LVD1024 Datasheet, PDF (12/23 Pages) THine Electronics, Inc. – 135MHz 67Bits LVDS Receiver | |||
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THC63LVD1024_Rev.2.4_E
AC Timing Diagrams (Continued)
tRCP
CLKOUT
DK=L
VCC/2
VCC/2
VCC/2
CLKOUT
DK=M
CLKOUT
DK=H
VCC/2
7
t--D-----O-----U-----T--
28
VCC/2
VCC/2
VCC/2
7
t--D-----O-----U-----T--
28
VCC/2
7
t--D-----O-----U-----T--
28
7
t--D-----O-----U-----T--
28
R/F=L
R/F=H
R/F=L
R/F=H
R/F=L
R/F=H
R1n, G1n, B1n
tRS
tRH
tRS
tRH
n = 0~9
HSYNC,VSYNC
DE
VCC/2
1st Pixel
Data
VCC/2
2nd Pixel
Data
VCC/2
CONT11,12
tDOUT
tDOUT
Fig6. CLKOUT Position and Setup/Hold Timing for Double Edge Output Mode
MODE<1:0>=LH, MODE2=H
RCLK+
(Differential)
Ryx+/-
x=1,2
y= A, B, C, D, E
Vdiff = 0V
tRCIP
Vdiff = 0V
Ryx3â Ryx2â Ryx1â Ryx0â Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1 Ryx0 Ryx6ââ
Previous Cycle
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
Current Cycle
Next Cycle
Fig7. LVDS Input Data Position
Copyright©2012 THine Electronics, Inc.
12/23
THine Electronics, Inc.
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