THC63LVD1024 Datasheet, PDF (1/23 Pages) THine Electronics, Inc. – 135MHz 67Bits LVDS Receiver

THC63LVD1024_Rev.2.4_E
THC63LVD1024
135MHz 67Bits LVDS Receiver
General Description
The THC63LVD1024 receiver is designed to support
Dual Link transmission between Host and Flat Panel
Display up to 1080p/QXGA resolutions. The
THC63LVD1024 converts the LVDS data streams back
into 67bits of CMOS/TTL data with falling edge or ris-
ing edge clock for convenient with a variety of LCD
panel controllers.
In Dual Link, data transmit clock frequency of
135MHz, 67bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 1.1Gbytes per
second.
Features
• Wide dot clock range suited for TV Signal(480i-
1080p), PC Signal(VGA-QXGA)
Dual LVDS port IN/Dual TTL port Out Mode:
8 - 135MHz(CLKOUT)
Dual LVDS port IN/Single TTL port Out Mode:
40 - 150MHz(CLKOUT)
• PLL requires No external components
• Flexible Input/Output mode
1. Single/Dual LVDS port IN /Single/Dual TTL port OUT
2. Double Edge output
• 50% output clock duty cycle
• TTL clock edge selectable
• TTL clock output timing programmable(3 step)
• 2 Output data mapping for simplifying PCB layout.
• Power down mode
• Low power single 3.3V CMOS design
• 144pin LQFP Exposed PAD
Block Diagram
LVDS INPUT
RA1 +/-
LVDS INPUT
Port1
RB1 +/-
RC1 +/-
RD1 +/-
RE1 +/-
LVDS INPUT
Port2
RA2 +/-
RB2 +/-
RC2 +/-
RD2 +/-
RE2 +/-
RCLK +/-
(8 to 135MHz)
/PDWN
MODE[2:0]
DK
R/F
O/E
MAP
Copyright©2012 THine Electronics, Inc.
35
35
PLL
1/23
R1[9:0]
32
G1[9:0]
B1[9:0]
CONT1[2:1]
TTL OUTPUT
Port1
R2[9:0]
32
G2[9:0]
B2[9:0]
TTL OUTPUT
CONT2[2:1]
Port2
3
Hsync
Vsync
DE
RECEIVER CLOCK OUT
(8 to 150MHz)
THine Electronics, Inc.