THC63LVD1024 Datasheet, PDF (11/23 Pages) THine Electronics, Inc. – 135MHz 67Bits LVDS Receiver

THC63LVD1024_Rev.2.4_E
AC Timing Diagrams
TTL Output
C_L=8pF
80%
20%
80%
20%
TTL Output Load
t_TLH
t_THL
Fig3. CMOS/TTL Output Load and Transition Time
t_RCP
t_RCH
t_RCL
CLKOUT
V_CC/2
V_CC/2
V_CC/2
V_CC/2
Fig4. CLKOUT Period and High/Low Time
CLKOUT
DK=L
V_CC/2
t_RCP
V_CC/2
V_CC/2
R/F=L
R/F=H
CLKOUT
DK=M
CLKOUT
DK=H
Rxn, Gxn, Bxn
x = 1,2
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
CONT21,22
V_CC/2
6t--D-----O-----U-----T-- ^or 7 ^{t--D-----O-----U-----T--}
28
28
V_CC/2
t_RS
V_CC/2
6t--D-----O-----U-----T-- ^or 7t--D-----O-----U-----T--
28
28
t_RH
V_CC/2
t_DOUT
Fig5. CLKOUT Position and Setup/Hold Timing
R/F=H
R/F=L
R/F=L
R/F=H
Copyright©2012 THine Electronics, Inc.
11/23
THine Electronics, Inc.