71M6511 Datasheet, PDF (51/95 Pages) Teridian Semiconductor Corporation – Single-Phase Energy Meter IC

71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
Power-Up: After power-up, the 71M6511/6511H is in reset as long as V1 < VBIAS. As soon as V1 exceeds VBIAS, the reset
timer is started which takes the MPU out of reset after 4100 oscillator cycles (see Figure 20). The MPU then initiates its pre-
boot phase lasting 32 cycles. The supply current will be low but not zero during power-up. It will increase, once V1 exceeds
VBIAS and will increase to the nominal value once the preboot phase starts. The supply current may then be reduced under
firmware control, following the steps specified in Battery Operation and Power Save Modes.
V2P5
V1
POWER PWR
DOWN ^UP
RESET TIMER
V1 > VBIAS
125ms
V3P3
PRE-
BOOT
1ms
FIRMWARE HAS CONTROL OVER CHIP...
SUPPLY CURRENT
3.3V
1.5V
0V
nominal
0mA
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up
Battery Operation
When V1 is lower than VBIAS, the external battery will power the following parts of the 71M6511/6511H:
• RTC
• Crystal oscillator circuitry
• MPU XRAM
• WD_OVF bit
Power Save Modes
In normal mode of operation, running on 3.3V supply, various resources of the 71M6511/6511H may be shut down by the MPU
firmware in order to reduce power consumption while other essential resources such as UARTs may remain active. Table 60
outlines these resources and their typical current consumption (based on initial condition MPU_DIV = 0).
Power Saving Measure
Software Control
Typical
Savings
Disable the CE
Disable the ADC
CE_EN = 0
ADC_DIS = 1
0.16mA
1.8mA
Disable clock test output CKTEST
CKOUTDIS = 1
0.6mA
Disable emulator clock
Set flash read pulse timing to 33 ns
Disable the LCD voltage boost circuitry
ECK_DIS = 1 *)
FLASH66Z =1
LCD_BSTEN = 0
0.1mA
0.04mA
0.9mA
Disable RTM outputs
RTM_EN = 0
0.01mA
Increase the clock divider for the MPU
MPU_DIV = X
0.4mA/MHz
*) This bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part with the ICE interface and thus
preclude flash erase and programming operations.
Table 60: Power Saving Measures
Page: 51 of 95
© 2005-2007 TERIDIAN Semiconductor Corporation
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