71M6511 Datasheet, PDF (24/95 Pages) Teridian Semiconductor Corporation – Single-Phase Energy Meter IC

71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
Bit
S1CON.7
S1CON.5
S1CON.4
S1CON.3
S1CON.2
S1CON.1
S1CON.0
Symbol
SM
SM21
REN1
TB81
RB81
TI1
RI1
Function
Sets the baud rate for UART1
SM
Mode
Description
Baud Rate
0
A
9-bit UART
variable
1
B
8-bit UART
variable
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9^th transmitted data bit in Mode A. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3, it is the 9^th data bit received. In Mode B, if sm21 is 0,
rb81 is the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial
transfer. Must be cleared by software.
Receive interrupt flag, set by hardware after completion of a serial
reception. Must be cleared by software
Table 18: The S1CON Bit Functions
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer
operations.
In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU
clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0
and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes 2 machine cycles
to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the
duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used
to select the appropriate mode.
Timer/Counter Mode Control register (TMOD):
MSB
LSB
GATE C/T
M1
M0
GATE
C/T
M1
M0
Timer 1
Timer 0
Table 19: The TMOD Register
Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON register (see Table 22 and Table 23) start their associated timers when
set.
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