SM5964 Datasheet, PDF (9/28 Pages) SyncMOS Technologies,Inc – 8 - bit single chip microcontroller with 64KB flash & 1K byte RAM embedded

SyncMOS Technologies Inc.
July 2002
SM5964
Data bank select enable bit BSE = 1 enables the data bank select function
Data bank select enable bit BSE = 0 disables the data bank select function
BS[3:0] setting will map $040~$07F RAM space to entire 1k byte on-chip RAM space.
Internal RAM Control Register (RCON, $85)
bit-7
Read:
Write:
Unused
Reset value:
*
Note: “R” means reserved
Unused
*
Unused
*
Unused
*
Unused
*
Unused
*
RAMS1
0
bit-0
RAMS0
0
SM5964 has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruc-
tion MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1, RAMS0) of
RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0).
System Control Register (SCONF, $BF)
Read:
Write:
Reset value:
bit-7
WDR
0
Unused
*
Unused
*
Unused
*
Unused
*
ISPE
0
OME
1
bit-0
ALEI
0
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
ISPE: ISP function enable bit
OME: 768 byte on-chip RAM enable bit
ALEI: ALE output inhibit bit, to reduce EMI
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 768 byte RAM. The default setting of OME bit is 1
(enable).
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow.
User should check WDR bit whenever unpredicted reset happened.
2. Port 4 for PLCC or QFP package :
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is
located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/28
Ver 1.0
PID 5964 07/02