SM5964 Datasheet, PDF (16/28 Pages) SyncMOS Technologies,Inc – 8 - bit single chip microcontroller with 64KB flash & 1K byte RAM embedded

SyncMOS Technologies Inc.
July 2002
SM5964
PDIV1
0
0
1
1
PDIV0
0
1
0
1
Divider
2
4
8
16
SPWM clock, Fosc=20MHz
10MHz
5MHz
2.5MHz
1.25MHz
SPWM Data Register (SPWMD[4:0], $AC, $A4 ~$A7)
SPWM clock, Fosc=24MHz
12MHz
6MHz
3MHz
1.5MHz
Read:
Write:
Reset value:
bit-7
SPWMD
[4:0]4
0
SPWMD
[4:0]3
0
SPWMD
[4:0]2
0
SPWMD
[4:0]1
0
SPWMD
[4:0]0
0
BRM
[4:0]2
0
BRM
[4:0]1
0
bit-0
BRM
[4:0]0
0
SPWMD[4:0][4:0] : content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[4:0][2:0] : will insert certain narrow pulses among an 8-SPWM-cycle frame
N = BRM[4:0][2:0]
XX1
X1X
1XX
Number of SPWM cycles inserted in an 8-cycle frame
1
2
4
Example of SPWM timing diagram :
MOV SPWMD0 , #83H ; SPWMD0[4:0]=10h (=16T high, 16T low), BRM0[2:0] = 3
MOV P1CON , #08H
; Enable P1.3 as PWM output pin
1st cycle frame 2nd cycle frame 3rd cycle frame 4th cycle frame 5th cycle frame 6th cycle frame 7th cycle frame 8th cycle frame
32T
32T
32T
32T
32T
32T
32T
32T
16T
16T
16T
16T
16T
16T
16T
16T
1T
1T
1T
(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
SPWM clock = 1 / T = Fosc / 2^(PDIV+1)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(PDIV+1)]/32
If user use Fosc=20MHz, PDIV[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/28
Ver 1.0
PID 5964 07/02