SM5964 Datasheet, PDF (14/28 Pages) SyncMOS Technologies,Inc – 8 - bit single chip microcontroller with 64KB flash & 1K byte RAM embedded

SyncMOS Technologies Inc.
July 2002
SM5964
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC. This will clear the content of the 16-bit counter and let
the counter re-start to count from the beginning.
4.1 Watch Dog Timer Registers: WDTC and SCONF
Watch Dog Timer Register- WDT Control Register (WDTC, $9F)
bit-7
bit-0
Read:
Write:
WDTE Unused CLEAR Unused Unused
PS2
PS1
PS0
Reset value:
0
*
0
*
*
0
0
0
WDTE: Watch Dog Timer enable bit
CLEAR: Watch Dog Timer counter clear bit
PS[2:0]: clock source divider bit
PS [2:0]
000
001
010
011
100
101
110
111
Divider (OSC in)
8
16
32
64
128
256
512
1024
Time Period (ms) @40MHZ
13.1
26.21
52.42
104.8
209.71
419.43
838.86
1677.72
Watch Dog Timer Register - System Control Register (SCONF, $BF)
Read:
Write:
Reset value:
bit-7
WDR
0
Unused
*
Unused
*
Unused
*
Unused
*
ISPE
0
OME
1
bit-0
ALEI
0
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever unpredicted reset happened
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/28
Ver 1.0
PID 5964 07/02