SMH4042A Datasheet, PDF (15/28 Pages) Summit Microelectronics, Inc. – Distributed Power Hot-Swap Controller for CompactPCI

SMH4042A
bit set to “1” it issues an acknowledge and transmits the 8-
Bit word stored at address location n+1. The current
address byte Read operation only accesses a single byte
of data. The Master holds the SDA line high (NACK) and
generates a Stop condition. At this point the SMH4042A
discontinues data transmission.
Random Address Read
Random address Read operations allow the Master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the Master
issues a Write command which includes the Start condi-
tion and the Slave address field (with the R/W bit set to
Write) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
SMH4042A to the desired address. After the word address
acknowledge is received by the Master, the Master
immediately reissues a Start condition followed by an-
other Slave address field with the R/W bit set to Read. The
SMH4042A will respond with an Acknowledge and then
transmit the 8 data bits stored at the addressed location.
At this point the Master issues a NACK and generates the
Stop condition. The SMH4042A discontinues data trans-
mission and reverts to its standby power mode.
Sequential Read
Sequential Reads can be initiated as either a current
address Read or a random access Read. The first word
is transmitted as with the other byte Read modes (current
address byte Read or random address byte Read);
however, the Master now responds with an Acknowledge,
indicating that it requires additional data from the
SMH4042A. The SMH4042A continues to output data for
each Acknowledge received. The Master terminates the
sequential Read operation with a NACK and a Stop.
During a sequential Read operation the internal address
counter is automatically incremented with each Acknowl-
edge signal. For Read operations all address bits are
incremented, allowing the entire array to be read using a
single Read command. After a count of the last memory
address the address counter will roll over and the memory
will continue to output data.
Data Download
The SMH4042A supports a proprietary mode of operation
specifically for the Hot Swap environment. After a power
on reset the internal address pointer is reset to 00. The
host or ASIC then only needs to issue a Read command
and then sequentially clock out data starting at address
00.
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
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