SMH4042A Datasheet, PDF (10/28 Pages) Summit Microelectronics, Inc. – Distributed Power Hot-Swap Controller for CompactPCI

SMH4042A
Over-current Circuit Breaker
The SMH4042A provides a circuit breaker function to
protect against short circuit conditions or exceeding the
supply limits. By placing a series resistor between the
host supply and the CBI pins, the breakers will trip
whenever the voltage drop across the series resistor is
greater than 50mV for more than 16µs.
The over-current detection circuit was designed to maxi-
mize protection while minimizing false alarms. The most
critical period of time is during the power-on sequence
when the backend circuits are first being energized. If the
card has a faulty component or shorted traces, the time
to shut off should be minimal. However, if the board has
been operational for a long period of time the likelihood of
a catastrophic failure occurring is quite low. Therefore,
the SMH4042A employs two different sampling schemes.
During power-up the device will sample the current every
500ns. If eight consecutive over-current conditions are
detected the VGATE outputs will immediately be shut
down. This provides an effective response time of 4µs.
During normal operation, after the FETs have been turned
on, the sampling rate will be adjusted to 2µs, thus
providing an effective response time of 16µs.
Also see Figure 3.
RESET CONTROL
While in the power sequencing mode, the reset outputs
are the last to be released. When they are released all
conditions of a successful power-up sequence must have
been met:
1) VCC and HST_3V_MON are at or above their respec-
tive VTRIP levels;
2) BD_SEL# inputs are low;
3) CARD_3V_MON and CARD_5V_MON are at or above
their respective trip levels;
4) PWR_EN is high; and
5) PCI_RST is high.
The PCI-RST# input must be high for the reset outputs to
be released. Assuming all of the conditions listed above
have been met and PCI_RST# is high and tPURST has
expired, a low input of greater than 40ns duration on the
PCI_RST# input will initiate a reset cycle. The duration of
the reset cycle will be determined by the PCI_RST# input.
If PCI_RST# low is shorter than tPURST, the reset outputs
will be driven active for tPURST. If PCI_RST# is longer than
tPURST the reset outputs will remain active until PCI_RST#
is released.
Also see Figure 4.
PCI_RST#
t_PRLPR
LOCAL_PCI_RST#
LOCAL_PCI_RST
t_PURST
t_PURST
Figure 4. Host-Initiated Reset Timing
2070 Fig04
10
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.