SMH4042A Datasheet, PDF (11/28 Pages) Summit Microelectronics, Inc. – Distributed Power Hot-Swap Controller for CompactPCI

SMH4042A
BUS INTERFACE
GENERAL DESCRIPTION
The I²C bus is a two-way, two-line serial communication
between different integrated circuits. The two lines are:
a serial Data line (SDA) and a serial Clock line (SCL). All
Summit Microelectronics parts support a 100kHz clock
rate, and some support the alternative 400kHz clock.
Check Table 2 for the value of fSCL. The SDA line must
be connected to a positive supply by a pull-up resistor
located on the bus. Summit parts have a Schmitt input on
both lines. See Figure 5 and Table 2 for waveforms and
timing on the bus. One bit of Data is transferred during
each Clock pulse. The Data must remain stable when the
Clock is high.
tR
tF
tHIGH
tLOW
SCL
tSU:SDA
SDA In
tHD:SDA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tAA
tDH
SDA Out
Figure 5. I²C Timing Diagram
2070 Fig05
Symbol
Parameter
Conditions
Min.
f_SCL
t_LOW
t_HIGH
t_BUF
t_SU:STA
t_HD:STA
t_SU:STO
t_AA
t_DH
t_R
t_F
t_SU:DAT
t_HD:DAT
TI
SCL clock frequency
0
Clock low period
4.7
Clock high period
4.0
Bus free time (1)
Before new transmission
4.7
Start condition setup time
4.7
Start condition hold time
4.0
Stop condition setup time
4.7
Clock edge to valid output SCL low to valid SDA (cycle n)
0.2
Data Out hold time
SCL low (cycle n+1) to SDA change 0.2
SCL and SDA rise time (1)
SCL and SDA fall time (1)
Data In setup time
250
Data In hold time
0
Noise filter SCL and SDA Noise suppression
t_WR
Write cycle time
Note 1 - Guaranteed by Design
Table 2. I²C AC Operating Characteristics
Typ. Max. Units
100 kHz
µs
µs
µs
µs
µs
µs
3.5 µs
µs
1000 ns
300 ns
ns
ns
100
ns
5 ms
2037 Table02 2.0
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
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