SMH4042A Datasheet, PDF (14/28 Pages) Summit Microelectronics, Inc. – Distributed Power Hot-Swap Controller for CompactPCI

SMH4042A
MEMORY OPERATION
WRITE OPERATIONS
The SMH4042A allows two types of Write operations to its
a 512 x 8 array: byte Write and page Write. A byte Write
operation writes a single byte during the nonvolatile Write
period (tWR). The page Write operation allows up to 16
bytes in the same page to be written during tWR.
Write Cycle
In Progress
Issue Start
Byte Write
After the slave address is sent (to identify the slave
device, and a Read or Write operation), a second byte is
transmitted which contains the 8 bit address of any one
of the 512 words in the array. Upon receipt of the word
address the SMH4042A responds with an Acknowledge.
After receiving the next byte of data, it again responds with
an Acknowledge. The master then terminates the transfer
by generating a Stop condition, at which time the
SMH4042A begins the internal write cycle. The
SMH4042A inputs are disabled while the internal write
cycle is in progress, and the device will not respond to any
requests from the Master.
Page Write
The SMH4042A is capable of a 16-byte page Write opera-
tion. It is initiated in the same manner as the byte-Write
operation, but, instead of terminating the Write cycle after
the first data word, the Master can transmit up to 15 more
bytes of data. After the receipt of each byte the SMH4042A
will respond with an Acknowledge.
The SMH4042A automatically increments the address for
subsequent data words. After the receipt of each word the
low order address bits are internally incremented by one.
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generating the Stop condition, the address counter will roll
over and the previously written data will be overwritten.
As with the byte-Write operation, all inputs are disabled
during the internal write cycle. Refer to Figure 5 for the
address, Acknowledge and data transfer sequence.
Issue Slave
Address and
R/W = 0
Issue Stop
ACK
Returned
Yes
Next
Operation
a Write?
Yes
Issue
Address
No
No
Issue Stop
Proceed
With
Write
Await
Next
Command
2070 Flow02
Flow Chart 2. Polling
READ OPERATIONS
There are two different read options:
1. Current Address Byte Read
2. Random Address Byte Read
Acknowledge Polling
When the SMH4042A is performing an internal Write
operation it will ignore any new Start conditions. Since the
device will only return an acknowledge after it accepts the
Start, the part can be continuously queried until an
acknowledge is issued, indicating that the internal write
cycle is complete. See Flow Chart 2 for the proper
sequence of operations for polling.
Current Address Read
The SMH4042A contains an internal address counter
which maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a Read or Write) was to address location n, the next Read
operation would access data from address location n+1
and increment the current address pointer. When the
SMH4042A receives the Slave address field with the R/W
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2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.