SMH4042A Datasheet, PDF (12/28 Pages) Summit Microelectronics, Inc. – Distributed Power Hot-Swap Controller for CompactPCI

SMH4042A
Start and Stop Conditions
Both Data and Clock lines remain high when the bus is not
busy. Data transfer between devices may be initiated with
a Start condition only when SCL and SDA are high. A high-
to-low transition of the Data line while the Clock line is high
is defined as a Start condition. A low-to-high transition of
the Data line while the Clock line is high is defined as a
Stop condition. See Figure 6.
SCL
START
Condition
STOP
Condition
SCL
1
2
3
8
9
SDA
Trans
SDA
Rec
ACK
2070 Fig07
Figure 7. Acknowledge Timing
leave the Data line high for a NACK. This will cause the
Summit part to stop sending data, and the Master will
issue a Stop on the clock pulse following the NACK.
SDA In
2070 Fig06
In the case of a Write to a Summit part the Master will send
a Stop on the clock pulse after the last Acknowledge. This
will indicate to the Summit part that it should begin its
internal non-volatile write cycle.
Figure 6. I²C Start and Stop Timing
Protocol
The protocol defines any device that sends data onto the
bus as a Transmitter, and any device that receives data
as a Receiver. The device controlling data transmission
is called the Master, and the controlled device is called
the Slave. In all cases the Summit Microelectronic
devices are Slave devices, since they never initiate any
data transfers.
Acknowledge
Data is always transferred in 8-Bit bytes. Acknowledge
(ACK) is used to indicate a successful data transfer. The
Transmitting device will release the bus after transmitting
eight bits. During the ninth clock cycle the Receiver will
pull the SDA line low to Acknowledge that it received the
eight bits of data (See Figure 7). The termination of a
Master Read sequence is indicated by a non-Acknowl-
edge (NACK), where the Master will leave the Data line
high.
In the case of a Read from a Summit part, when the last
byte has been transferred to the Master, the Master will
Basic Read and Write
The first byte from a Master is always made up of a seven
bit Slave address and the Read/Write bit. The R/W bit tells
the Slave whether the Master is reading data from the bus
or writing data to the bus (1 = Read, 0 = Write). The first
four of the seven address bits are called the Device Type
Identifier (DTI). The DTI for the SMH4042A is 1010BIN. The
next two bits are used to select one-of-four possible
devices on the bus. The next bit is the block select bit.
The SMH4042A will issue an Acknowledge after recogniz-
ing a Start condition and its DTI.
In the Read mode the SMH4042A transmits eight bits of
data, then releases the SDA line, and monitors the line for
an Acknowledge signal. If an Acknowledge is detected,
and no Stop condition is generated by the Master, the
SMH4042A will continue to transmit data. If an Acknowl-
edge is not detected (NACK), the SMH4042A will terminate
further data transmission. See Figure 9.
In the Write mode the SMH4042A receives eight bits of
data, then generates an Acknowledge signal. It will
continue to generate ACKs until a Stop condition is
generated by the Master. See Figure 10.
SCL
SDA
12
1
2
3
4
5
6
7
8
9
1
0
1
0
x
x
x
R/W
ACK
2070 Fig08
Figure 8. Typical Master Address Byte Transmission
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.