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STR720 Datasheet, PDF (97/401 Pages) STMicroelectronics – ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
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STR720 - DMA CONTROLLER (DMAC)
Interrupt Status Register (DMAStatus)
Address Offset: F8h
Reset value: 0000h
15 14 13 12 11 10 9
8
7
65
43
2
1
0
reserved
ACT3 ACT2 res. res.d ERR3 ERR2 res. res. INT3 INT2 res. res.
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DMAStatus provides status information regarding the DMA Controller. This is a read-only
register.
Bits 1:0 = Reserved. They must always be written to 0.
Bit 2 = INT2: Data stream 2 interrupt flag
When a transfer end event occurs on stream 2, this bit will be set to ‘1’ and if SIM2 bit of
DMAMask has also set to ‘1’ by software then a DMA interrupt request will be generated. This
flag is cleared by writing ‘1’ in SIC2 bit of DMAClear register.
Bit 3 = INT3: Data stream 3 interrupt flag
When a transfer end event occurs on stream 3, this bit will be set to ‘1’ and if SIM3 bit of
DMAMask has also set to ‘1’ by software then a DMA interrupt request will be generated. This
flag is cleared by writing ‘1’ in SIC3 bit of DMAClear register.
Bits 5:4 = Reserved. They must always be written to 0.
Bit 6 = ERR2: Data stream 2 error flag
When a transfer error event occurs on stream 2, this bit will be set to ‘1’ and if SEM2 bit of
DMAMask has also set to ‘1’ by software then a DMA interrupt request will be generated. This
flag is cleared by writing ‘1’ in SEC2 bit of DMAClear register.
Bit 7 = ERR3: Data stream 3 error flag
When a transfer error event occurs on stream 3, this bit will be set to ‘1’ and if SEM3 bit of
DMAMask has also set to ‘1’ by software then a DMA interrupt request will be generated. This
flag is cleared by writing ‘1’ in SEC3 bit of DMAClear register.
Bits 9:8 = Reserved. They must always be written to 0.
Bit 10 = ACT2: Data stream 2 status
1: Data stream 2 is active.
0: Data stream 2 is not active
Bit 11 = ACT3: Data stream 3 status
1: Data stream 3 is active.
0: Data stream 3 is not active
Bit 15:12 = Reserved. They must be always written to ‘0’
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