STR720 Datasheet, PDF (170/401 Pages) STMicroelectronics – ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES

STR720 - UART
Figure 20. 8-bit data frames
start _D0
bit _LSB
D1
D2
D3 D4 D5
D6
8th 1st 2nd
bit stop stop
bit bit
- Data bit (D7)
- Parity bit
Nine bit data frames (see Figure 21) either consist of:
• nine data bits D0-8 (by setting the Mode bit field to 100);
• eight data bits D0-7 plus an automatically generated parity bit (by setting the Mode bit
field to 111);
• eight data bits D0-7 plus a wake-up bit (by setting the Mode bit field to 101).
Figure 21. 9-bit data frames
start _D0
bit _LSB
D1
D2
D3
D4
D5
D6
D7
9th 1st 2nd
bit stop stop
bit bit
- Data bit (D8)
- Parity bit
- Wake-up bit
Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An
even parity bit will be set, if the modulo-2-sum of the eight data bits is 1. An odd parity bit will
be cleared in this case.
In wake-up mode, received frames are only transferred to the receive buffer register if the
ninth bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and
no data will be transferred.
This feature may be used to control communication in multi-processor systems. When the
master processor wants to transmit a block of data to one of several slaves, it first sends out
an address byte which identifies the target slave. An address byte differs from a data byte in
that the additional ninth bit is a 1 for an address byte and a 0 for a data byte, so no slave will
be interrupted by a data byte. An address byte will interrupt all slaves (operating in 8-bit data
+ wake-up bit mode), so each slave can examine the 8 least significant bits (LSBs) of the
received character (the address). The addressed slave will switch to 9-bit data mode, which
enables it to receive the data bytes that will be coming (with the wake-up bit cleared). The
slaves that are not being addressed remain in 8-bit data + wake-up bit mode, ignoring the
following data bytes.
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