STR720 Datasheet, PDF (80/401 Pages) STMicroelectronics – ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES

STR720 - WAKE-UP INTERRUPT UNIT (WIU)
8.6.2 Simultaneous Setting of Pending Bits
It is possible that several simultaneous wake-up event set different pending bits. In order to
accept subsequent events on external wake-up/interrupt lines, once the first interrupt routine
has been executed, it is necessary to clear at least one pending bit (the corresponding
pending bit in WUPRx register): this operation allows to generate a rising edge on the internal
line (if there is at least one more pending bit set and not masked) and so to set the interrupt
controller pending bit again. A further interrupt on the same channel of the interrupt controller
will be serviced depending on the status of its mask bit. Two possible situations may arise:
1 The user chooses to reset all pending bits: no further interrupt requests will be generated
on channel. In this case the user has to:
• Reset the interrupt controller mask bit (to avoid generating a spurious interrupt request
during the next reset operation on the WUPR register)
• Reset WUPR register.
2 The user chooses to keep at least one pending bit active: at least one additional interrupt
request will be generated on the same interrupt controller channel. In this case the user
has to reset the desired pending bits. This operation will generate a rising edge on the
interrupt controller channel and the corresponding pending bit will be set again. An
interrupt on this channel will be serviced depending on the status of corresponding mask
bit.
8.6.3 Dealing with level-active signals as interrupt lines
It must be noticed that using signals generated for level sensitive interrupt lines through the
WIU which supports edge-sensitive inputs only, has the consequence of requiring a special
handling during the interrupt response routine in order to avoid missing some events. Actually
it is better to clear the WIU pending bit as first action, so to be able to detect any subsequent
edge of the level-sensitive line which could be otherwise skipped if another event occurs while
still processing a previously issued one, leaving the WIU line insensitive to any further event
occurring on that line. This situation can happen with external interrupt lines, for example, and
it is peculiar of lock/unlock events detection. As an example the safest sequence to be
followed in the case of a lock/unlock event is reported below:
1 Clear WIU pending bit corresponding to the used line (WUPR bit 6).
2 Clear EIC pending bit corresponding to WIU (IPR0 bit 2, if used).
3 Clear both RCCU pending bits, once the nature of the interrupting event has been
detected and taken proper care of (LOCK_I/ULOCK_I bits of CLKFLAG).
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