STR720 Datasheet, PDF (107/401 Pages) STMicroelectronics – ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES

STR720 - DRAM CONTROLLER (DRAMC)
Bank 1 SDRAM Configuration Register High (SDRAM1ConfigHi)
Address Offset: 14h
Reset value: 0000h
15 14 13 12 11 10 9
8
7
65
43
2
1
0
reserved
MIWE MIAA MISA
wo wo wo
The Bank 1 SDRAM Configuration Register High (SDRAM1ConfigHi) is a 16-bit write only
control register used to configure the SDRAM device of external region 1 (Bank 1). The
SDRAM1ConfigHi control bits are described below.
Bit 15:3 reserved (should be written as zero).
Bit 2
MIWE: Memory Interface Write Enable.
This bit allows to control directly the value on the SDRAM write enable line. When
it is written to ‘1’ the corresponding memory pin will be asserted to ‘0’ for one clock
period. This is a write-ony bit.
Bit 1
MIAA: Memory Interface Access Active (nCAS).
This bit allows to control directly the value on the SDRAM column address strobe
line. When it is written to ‘1’ the corresponding memory pin will be asserted to ‘0’
for one clock period. This is a write-ony bit.
Bit 0
MISA: Memory Interface Setup Active (nRAS).
This bit allows to control directly the value on the SDRAM row address strobe line.
When it is written to ‘1’ the corresponding memory pin will be asserted to ‘0’ for one
clock period. This is a write-ony bit.
Bank 2 SDRAM Configuration Register Low (SDRAM2ConfigLo)
Address Offset: 18h
Reset value: 0000h
15 14 13 12 11 10 9
8
7
65
43
2
1
0
reserved
MIAB
wo
The Bank 2 SDRAM Configuration Register Low (SDRAM2ConfigLo) is a 16-bit write only
control register used to configure the SDRAM device of external region 2 (Bank 2).
The SDRAM2ConfigLo control bits are the same as SDRAM1ConfigLo register.
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