STR720 Datasheet, PDF (355/401 Pages) STMicroelectronics – ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES

STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR)
CGC Peripheral Under Reset register 1 (CGC-PUR1)
Address: 0xF000_2C04
Reset value: 0x0023
15 14 13 12 11 10 9
8
7
65
43
2
1
0
Reserved
P11UR P10UR Reserved
P7UR P6UR P5UR REs. P3UR P2UR P1UR P0UR
-
rw rw
-
rw rw rw - rw rw rw rw
This register configures the reset line status for each of the controlled AHB/S-APB
peripherals. Each peripheral can be used only when its corresponding reset line is not active.
Bits 15:12, 9:8, 4 = Reserved. These bits must be always written to 0.
Bits 11:10, 7:5, 3:0 = PxUR: Peripheral x Under Reset
0: Peripheral x is under reset.
1: Peripheral x is operating normally.
The following table lists the correspondence between each controllable peripheral and the
CGC-PUR1 register bits along with their reset value.
Table 75. CGC-PUR1 bit assignment
CGC-PUR1
Bit
P0UR
EMI
P1UR
DRAMC
P2UR
DMAC
P3UR
ATAPI
P5UR
EIC
P6UR
GPIO-P3
P7UR
GPIO-P4
P10UR
WIU
P11UR
RTC
Affected
peripheral
Reset
status
Operative
Operative
Under reset
Under reset
Operative
Under reset
Under reset
Under reset
Under reset
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