ST10F280 Datasheet, PDF (94/186 Pages) STMicroelectronics – 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM

ST10F280
Bit
DP6.y
Function
Port direction register DP6 bit y
DP6.y = 0: Port line P6.y is an input (high-impedance)
DP6.y = 1: Port line P6.y is an output
ODP6 (F1CEh / E7h)
15 14 13 12 11 10 9
-
-
-
-
-
-
-
ESFR
Reset Value: - - 00h
8
7
6
5
4
3
2
1
0
- ODP6.7ODP6.6ODP6.5 ODP6.4 ODP6.3 ODP6.2 ODP6.1 ODP6.0
RW RW RW RW RW RW RW RW
Bit
ODP6.y
Function
Port 6 Open Drain control register bit y
ODP6.y = 0: Port line P6.y output driver in push/pull mode
ODP6.y = 1: Port line P6.y output driver in open drain mode
12.8.1 - Alternate Functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control registers
(BUSCON4...BUSCON0) can be output on the 5 pins of Port 6. The number of chip select signals is
selected via PORT0 during reset. The selected value can be read from bitfield CSSEL in register RP0H
(read only) e.g. in order to check the configuration during run time. The table below summarizes the alter-
nate functions of Port 6 depending on the number of selected chip select lines (coded via bitfield CSSEL).
Table 18 : Port 6 Alternate Functions
Port 6 Pin
Altern. Function
CSSEL = 10
Altern. Function
CSSEL = 01
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
Gen. purpose I/O
Gen. purpose I/O
Gen. purpose I/O
HOLD External hold request input
HLDA Hold acknowledge output
BREQ Bus request output
Altern. Function
CSSEL = 00
Chip select CS0
Chip select CS1
Chip select CS2
Gen. purpose I/O
Gen. purpose I/O
Altern. Function
CSSEL = 11
Chip select CS0
Chip select CS1
Chip select CS2
Chip select CS3
Chip select CS4
Figure 44 : Port 6 I/O and Alternate Functions
Alternate Function
a)
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Port 6
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
General Purpose Input/Output
BREQ
HLDA
HOLD
CS4
CS3
CS2
CS1
CS0