ST10F280 Datasheet, PDF (166/186 Pages) STMicroelectronics – 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM

ST10F280
Table 41 : Multiplexed Bus Characteristics
Symbol
Parameter
Max. CPU Clock
= 40MHz
min.
max.
t₄₂
CC ALE fall. edge to RdCS, WrCS
7 + t_A
(with RW delay)
t₄₃ CC ALE fall. edge to RdCS, WrCS -5.5 + t_A
(no RW delay)
t₄₄ CC Address float after RdCS,
–
WrCS (with RW delay)
1
t₄₅ CC Address float after RdCS,
–
WrCS (no RW delay)
1
t₄₆ SR RdCS to Valid Data In
–
(with RW delay)
t₄₇ SR RdCS to Valid Data In
–
(no RW delay)
t₄₈ CC RdCS, WrCS Low Time
(with RW delay)
15.5 + t_C
t₄₉ CC RdCS, WrCS Low Time
(no RW delay)
28 + t_C
t₅₀ CC Data valid to WrCS
10 + t_C
t₅₁ SR Data hold after RdCS
0
t₅₂ SR Data float after RdCS
1
–
t₅₄ CC Address hold after
RdCS, WrCS
6 + t_F
t₅₆ CC Data hold after WrCS
6 + t_F
Note: 1. Partially tested, guaranted by design characterization.
–
–
0
12.5
4 + t_C
16.5 + t_C
–
–
–
–
16.5 + t_F
–
–
Variable CPU Clock
1/2 TCL = 1 to 40MHz
min.
TCL - 5.5+ t_A
max.
–
ns
-5.5 + t_A
–
ns
–
0
ns
–
TCL
ns
–
2 TCL - 21 + t_C ns
–
3 TCL - 21 + t_C ns
2 TCL - 9.5 + t_C
–
ns
3 TCL - 9.5 + t_C
–
ns
2 TCL - 15+ t_C
–
ns
0
–
ns
–
2 TCL - 8.5+t_F ns
2 TCL - 19 + t_F
–
ns
2 TCL - 19 + t_F
–
ns
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