ST10F280 Datasheet, PDF (178/186 Pages) STMicroelectronics – 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM

ST10F280
Figure 88 : CLKOUT and READY
CLKOUT
ALE
Running cycle 1)
t₃₂
t₃₃
t₃₀
t₃₄
t₃₁
READY
wait state
MUX / Tri-state 6)
t₂₉
7)
RD, WR
2)
Synchronous
t₃₅ t₃₆
t₃₅ t₃₆
READY
3)
3)
Asynchronous
t₅₈ t₅₉
t₅₈ t₅₉
t_{60 4)}
READY
3)
3)
t₃₇
5)
6)
Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling
point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because
CLKOUT is not enabled), it must fulfill t₃₇ in order to be safely synchronized. This is guaranteed, if READY is removed in response to
the command (see Note 4)).
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here.
For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this
delay is zero.
7. The next external bus cycle may start here.
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