RM0376 Datasheet, PDF (769/968 Pages) STMicroelectronics – This reference manual targets application developers

RM0376
Universal synchronous asynchronous receiver transmitter (USART)
Bit 3 ORECF: Overrun error clear flag
Writing 1 to this bit clears the ORE flag in the USARTx_ISR register.
Bit 2 NCF: Noise detected clear flag
Writing 1 to this bit clears the NF flag in the USARTx_ISR register.
Bit 1 FECF: Framing error clear flag
Writing 1 to this bit clears the FE flag in the USARTx_ISR register.
Bit 0 PECF: Parity error clear flag
Writing 1 to this bit clears the PE flag in the USARTx_ISR register.
28.8.10
Receive data register (USARTx_RDR)
Address offset: 0x24
Reset value: Undefined
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res. Res. Res. Res. Res. Res. Res.
RDR[8:0]
r
r
r
r
r
r
r
r
r
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 RDR[8:0]: Receive data value
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 221).
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.
28.8.11
Transmit data register (USARTx_TDR)
Address offset: 0x28
Reset value: Undefined
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res. Res. Res. Res. Res. Res. Res.
TDR[8:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
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