RM0376 Datasheet, PDF (360/968 Pages) STMicroelectronics – This reference manual targets application developers

Digital-to-analog converter (DAC)
RM0376
15.8.11 Dual DAC 8-bit right-aligned data holding register
(DAC_DHR8RD)
Address offset: 0x28
Reset value: 0x0000 0000
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACC2DHR[7:0]
DACC1DHR[7:0]
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Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
15.8.12
DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res. Res. Res. Res.
DACC1DOR[11:0]
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
15.8.13
DAC channel2 data output register (DAC_DOR2)
Address offset: 0x30
Reset value: 0x0000 0000
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res. Res. Res. Res.
DACC2DOR[11:0]
r
r
r
r
r
r
r
r
r
r
r
r
360/968
DocID025941 Rev 2