RM0376 Datasheet, PDF (190/968 Pages) STMicroelectronics – This reference manual targets application developers

Reset and clock control (RCC)
RM0376
7.3.6
Clock interrupt flag register (RCC_CIFR)
Address: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
Res.
16
Res.
15
Res.
14
Res.
13
Res.
12
Res.
11
Res.
10
Res.
9
Res.
8
CSS
HSEF
r
7
CSS
LSEF
r
6
HSI48
RDYF
r
5
MSI
RDYF
r
4
PLL
RDYF
r
3
HSE
RDYF
r
2
HSI16
RDYF
r
1
LSE
RDYF
r
0
LSI
RDYF
r
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 CSSHSEF: Clock Security System Interrupt flag
This bit is reset by software by writing the CSSHSEC bit. It is set by hardware in case of HSE
clock failure.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 7 CSSLSEF: LSE Clock Security System Interrupt flag
This bit is reset by software by writing the CSSLSEC bit. It is set by hardware in case of LSE
clock failure and the CSSLSE is set.
0: No failure detected on LSE clock failure
1: Failure detected on LSE clock failure
Bit 6 HSI48RDYF: HSI48 ready interrupt flag
This bit is reset by software by writing the HSI48RDYC bit. It is set by hardware when the
CSS becomes stable and the HSI48RDYIE is set.
0: No clock ready interrupt caused by HSI48 clock failure
1: Clock ready interrupt caused by HSI48 clock failure
Bit 5 MSIRDYF: MSI ready interrupt flag
This bit is reset by software by writing the MSIRDYC bit. It is set by hardware when the MSI
clock becomes stable and the MSIRDYIE is set.
0: No clock ready interrupt caused by MSI clock failure
1: Clock ready interrupt caused by MSI clock failure
Bit 4 PLLRDYF: PLL ready interrupt flag
This bit is reset by software by writing the PLLRDYC bit. It is set by hardware when the PLL
clock becomes stable and the PLLRDYIE is set.
0: No clock ready interrupt caused by PLL clock failure
1: Clock ready interrupt caused by PLL clock failure
Bit 3 HSERDYF: HSE ready interrupt flag
This bit is reset by software by writing the HSERDYC bit. It is set by hardware when the HSE
clock becomes stable and the HSERDYIE is set.
0: No clock ready interrupt caused by HSE clock failure
1: Clock ready interrupt caused by HSE clock failure
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