TDA7503 Datasheet, PDF (6/26 Pages) STMicroelectronics – DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

TDA7503
PIN DESCRIPTION (continued)
N.
Name
Type
Reset
Status (1)
Function
4
RESET
I/O
I
System Reset. A logic low level applied to RESET input initializes the
microcontroller. The micro is responsible for initializing the DSPs. If the
watchdog timer overflow occurs this pin is driven low for 1 watchdog
timer cycle. During Debug Mode if this pin is pulled low in while the
DBRQN line is pulled low then the DSP pointed to by the DBSEL pin will
be reset.
96 RXD(P3.0)
I/O
I
Microcontroller Standard Serial Interface (Asynchronous) Input Data. Or
GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.
97 TXD(P3.1)
I/O
I
Microcontroller Standard Serial Interface (Asynchronous) Output Data.
Or GPIO. This pin can also act as GPIO using the P3 and P3DIR
registers.
99 INT0(P3.2)
I/O
I
Microcontroller Interrupt 0. When pulled low, INT0 asserts a
microcontroller external interrupt. In addition, if this pin is pulled low
during powerdown this allows the M8051 to resume executing intructions
where it left off. This pin can also act as GPIO using the P3 and P3DIR
registers.
98 INT1(P3.3)
I/O
I
Microcontroller Interrupt 1. When pulled low, INT1 asserts a
microcontroller external interrupt. In addition, if this pin is pulled low
during powerdown this allows the M8051 to resume executing intructions
where it left off. This pin can also act as GPIO using the P3 and P3DIR
registers.
100 T0(P3.4)
I/O
I
Microcontroller Timer 0 External Input. Input event clock for timer 0, or
GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.
1
T1(P3.5)
I/O
I
Microcontroller Timer 1 External Input. Input event clock for timer 1, or
GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.
87 GPIO0(P1.0) I/O
I
Microcontroller General Purpose. This GPIO line can be configured to be
digital input or output by writing to the P1 and P1DIR registers.This pin is
tri-stated while the RESET pin is held low and is pulled low when RESET
is released. This pin will be pulled high when in IDLE or PWRDN modes.
88 GPIO1(P1.1) I/O
I
Microcontroller General Purpose. This GPIO line can be configured to be
digital input or output by writing to the P1 and P1DIR registers. At reset it
is configured as an input with the output tri-stated.
89 GPIO2(P1.2) I/O
I
Microcontroller General Purpose. This GPIO line can be configured to be
digital input or output by writing to the P1 and P1DIR registers. At reset it
is configured as an input with the output tri-stated.
92 GPIO3(P1.3) I/O
I
Microcontroller General Purpose. This GPIO line can be configured to be
digital input or output by writing to the P1 and P1DIR registers. At reset it
is configured as an input with the output tri-stated.
93 GPIO4(P1.4) I/O
I
Microcontroller General Purpose. This GPIO line can be configured to be
digital input or output by writing to the P1 and P1DIR registers. At reset it
is configured as an input with the output tri-stated.
94 GPIO5(P1.5) I/O
I
Microcontroller General Purpose. This GPIO line can be configured to be
digital input or output by writing to the P1 and P1DIR registers. At reset it
is configured as an input with the output tri-stated.
95 GPIO6(P1.6) I/O
I
Microcontroller General Purpose. This GPIO line can be configured to be
digital input or output by writing to the P1 and P1DIR registers. At reset it
is configured as an input with the output tri-stated.
7
SCLK
I/O
I
Microcontroller General Purpose. Each of the six GPIO lines can be
individually configured to be digital input or output by writing to the P1
and P1DIR registers. All GPIOs are configured to be inputs with the
outputs tri-stated except for P1.0. This pin is tri-stated during while the
RESET pin is held low and is pulled low when RESET is released. This
pin will be pulled high when in IDLE or PWRDN modes.
6
MOSI
I/O
I
Microcontroller SPI Master Output Slave Input Serial Data . Serial Data
Output for SPI type serial port when in SPI Master Mode and Serial Data
Input when in SPI Slave Mode.
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