TDA7503 Datasheet, PDF (14/26 Pages) STMicroelectronics – DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

TDA7503
MICRO MEMORY INTERFACE
Figure 9. Timing diagram for External Memory Interface
For the calculation of slowest access time allowed for a memory attached to the M8051, the
following diagram illustrates the timing constraints. Slowest access time allowed, tacc =
4*mclk - tad - tds, where the worst case address delay, tad = 30 ns, and the worst case data
setup time, tds = 20 ns.
mclk
XALE
XPSEN
OPLOAD
Address
Data
t _ad
t _acc
t _ds
GENERAL PURPOSE I/O (GPIO) INTERFACE
Timing
Characteristics
t_god XTI Edge to GPIO Out Valid (GPIO Out Delay Time)
t_goh XTI Edge to GPIO Out Not Valid (GPIO Out Hold Time)
t_gis GPIO In Valid to XTI Edge (GPIO In Set-up Time)
t_gih XTI Edge to GPIO In Not Valid (GPIO In Hold Time)
mclk = 20MHz _Unit
Min. Max.
--
26
ns
2
--
ns
10
--
ns
6
--
ns
Figure 10. GPIO Timing
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