TDA7503 Datasheet, PDF (20/26 Pages) STMicroelectronics – DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

TDA7503
Figure 19. DRAM Write Cycle.
DRA [8:0]
Row address 1
RAS
Column address 1 Column address 2
Row address 2
CAS
DWR
DRD[3:0]
nibble 1
nibble 2
FUNCTIONAL DESCRIPTION.
The Aladdin IC broken up into two distinct blocks.
One block contains the two DSP Cores and their
associated peripherals. The other contains the
M8051 Core and its associated peripherals. The
interface between the two blocks is the Host In-
terface.
24-BIT DSP CORE.
The two DSP cores are used to process the con-
verted analog audio data coming from the
CODEC chip via the SAI and return it for analog
conversion. Functions such as volume, tone, bal-
ance, and fader control, as well as spatial en-
hancement and general purpose signal process-
ing may be performed by the DSPs.
Some capabilities of the DSPs are listed below:
Single cycle multiply and accumulate with con-
vergent rounding and condition code genera-
tion
2 x 56-bit Accumulators
Double precision multiply
Scaling and saturation arithmetic
48-bit or 2 x 24-bit parallel moves
64 interrupt vector locations
Fast or long interrupts possible
Programmable interrupt priorities and masking
8 each of Address Registers, Address Offset
Registers and Address Modulo Registers
Linear, Reverse Carry, Multiple Buffer Modulo,
Multiple Wrap-around Modulo address arith-
metic
Post-increment or decrement by 1 or by offset,
Index by offset, predecrement address
Repeat instruction and zero overhead DO
loops
Hardware stack capable of nesting combina-
tions of 7 DO loops or 15 interrupts/subrou-
tines
Bit manipulation instructions possible on all
registers and memory locations. Also Jump on
bit test.
4 pin serial debug interface
Debug ccess to all internal registers, buses
and memory locations
5 word deep program address history FIFO
Hardware and software breakpoints for both
program and data memory accesses
Debug Single stepping, Instruction injection
and Disassembly of program memory
DSP PERIPHERALS
There are a number of peripherals that are tightly
coupled to the two DSP Cores. Except for the
memories and the Host Interface, a single periph-
eral is multiplexed to both of the DSP Cores. In
the case of the Host Interface(HI), for DSP to Mi-
cro communication, there are two identical pe-
ripheral blocks providing the same function to
both DSP Cores. Each of the peripherals are
listed below and described in the following sec-
tions.
256 x 24-Bit X-RAM.
256 x 24-Bit Y-RAM.
768 x 24-Bit Program RAM (1280 x 24 for
DSP1)
256 x 24-Bit Data X-ROM.
256 x 24-Bit Data Y-ROM.
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