TDA7503 Datasheet, PDF (10/26 Pages) STMicroelectronics – DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

TDA7503
SAI/SSI INTERFACE
Figure 1. SAI and SSI Timings
SDI0-3
Valid
LRCKR
SCKR
(RCKP=0)
t _sckpl
tdt
Valid
t _lrh
tlrs
tsdih
tsdis
t _sckr
Timing
t_sckr
t_dt
t_lrs
t_lrh
t_sdid
t_sdih
t_sckph
t_sckpl
Description
Minimum Clock Cycle
SCKR active edge to data out valid
LRCK setup time
LRCK hold time
SDI setup time
SDI hold time
Minimum SCK high time
Minimum SCK low time
Note TDSP = dsp master clock cycle time = 1/FDSP
Figure 2. SAI Interrupt protocol
LRCKT
Left
Right
TDE
Internal Flag set when left data written
to all enabled transmitters. If this internal
flag is set then right data must written
to data registers before the next
falling edge of LRCKT.
t _sckph
Value
3T_DSP+5
40
5
5
5
5
0.35 t_sckr
0.35 t_sckr
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Left
Right
TDE cleared when right data written
to all enabled transmitters.
LRCKR
RDR
10/26
Left
Right
Left
RDR cleared when right data read from
all enabled transmitters.
Internal Flag set when left data read
from all enabled receivers. If this internal
flag is set then right data must read
from data registers before the next
rising edge of LRCKR.
Right