TDA7503 Datasheet, PDF (3/26 Pages) STMicroelectronics – DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

TDA7503
PIN DESCRIPTION
N.
Name
Type
Reset
Status (1)
Function
11
LRCKR
I
–
Audio Serial Port Receive Left/Right Frame Sync. The Left/Right select
signal for received serial audio data. This signal has a frequency equal to
the audio sample rate.
12
SCLKR
I
–
Audio Serial Port Receive Bit Clock. SCLK clocks received digital audio
data into pins SDI0, SDI1, SDI2, and SDI3
16
SDI0
I
–
Stereo Digital Audio Data. SDI0 is a stereo digital audio data input pin
channel 0.
15
SDI1
I
–
Stereo Digital Audio Data. SDI1 is a stereo digital audio data input pin
channel 1.
14
SDI2
I
–
Stereo Digital Audio Data. SDI2 is a stereo digital audio data input pin
channel 2.
13
SDI3
I
–
Stereo Digital Audio Data / Serial Receive Data. SDI3 is a stereo digital
audio data input pin and is multiplexed with the SSI’s Serial Receive
Data Input channel 3.
25
LRCKT
I
–
Audio Serial Port Transmit Left/Right Frame Sync /Frame Sync. The
Left/Right select signal for transmitted serial audio data. This signal has a
frequency equal to the audio sample rate. This signal is multiplexed with
the SSI’s Frame Sync Input.
24
SCLKT
I
–
Audio Serial Port Transmit Bit Clock/SSI Serial Bit Clock. SCLK clocks
digital audio data out of pins SDO0, SDO1, SD02, SD03, and SD04. This
pin is multiplexed with the SSI’s serial bit clock.
21
SDO0
O
High Stereo Digital Audio Data. SDO0 is a stereo digital audio data output pin
channel 0.
20
SDO1
O
High Stereo Digital Audio Data. SDO1 is a stereo digital audio data output pin
channel 1.
19
SDO2
O
High Stereo Digital Audio Data. SDO2 is a stereo digital audio data output pin
channel 2.
18
SDO3
O
High Stereo Digital Audio Data. SDO3 is a stereo digital audio data output pin
channel 3.
17
SDO4
O
High Stereo Digital Audio Data /Serial Transmit Data. SDO4 is a stereo digital
audio data output pin and is multiplexed with the SSI’s Serial Transmit
Data Output channel 4.
34
SCANEN
I
–
SCAN Enable. Enable SCAN Path and MUXing of SCANIN and SCANOUT
Pins.
33
TESTEN
I
–
Test Enable. Enable Scan Mode Clocks. An active low signal will enable
the same clock to all scan chains. This pin also makes all latches
transparent.
49 SRA_D0/DRD0 I/O
I
DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM Data Line
0.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 0. When in DRAM Mode they act as the EMI data line 0.
48 SRA_D1/DRD1 I/O
I
DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM Data Line
1.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 1. When in DRAM Mode they act as the EMI data line 1.
47 SRA_D2/DRD2 I/O
I
DSP SRAM Multiplexed Address/Data Line 2/DSP DRAM Data Line
2.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 2. When in DRAM Mode they act as the EMI data line 2.
46 SRA_D3/DRD3 I/O
I
DSP SRAM Multiplexed Address/Data Line 3/DSP DRAM Data Line
3.When in SRAM Mode these pins act as the EMI multiplexed address
and data line 3. When in DRAM Mode they act as the EMI data line 3.
43 SRA_D4/DRA0 I/O
O, High DSP SRAM Multiplexed Address/Data Line 4/DSP DRAM Address Line
0. When in SRAM Mode these pins act as the EMI multiplexed address
and data line 4. When in DRAM Mode they act as the EMI address line 0.
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