M34A02 Datasheet, PDF (6/15 Pages) STMicroelectronics – 2 Kbit Serial SMBus EEPROM for ACR Card Configuration

M34A02
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC
BYTE WRITE
ACK
ACK
ACK
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
ACK
ACK
DEV SEL
BYTE ADDR DATA IN 1
DATA IN 2
DATA IN 3
R/W
ACK
ACK
DATA IN N
AI02804
Write Operations
Following a Start condition the bus master sends
a Device Select code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
6, and waits for one address byte. The device
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is taken High. Any Write instruction
with Write Control (WC) held High (during a period
of time from the Start condition until the end of the
address byte) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 5.
Each data byte in the memory has a 8-bit address.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10^th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time does not trigger
the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not
respond to any requests (and sends NoAck in
reply to them).
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC), the device replies with NoAck, and
the location is not modified. If, instead, the
addressed location is not Write-protected, the
device replies with Ack. The bus master
terminates the transfer by generating a Stop
condition, as shown in Figure 6.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b7-b4) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
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