STM8L151X6 Datasheet, PDF (52/146 Pages) STMicroelectronics – Operating conditions

Memory and register map
STM8L151x6/8 STM8L152x6/8
Address
0x00 52D2
0x00 52D3
0x00 52D4
to
0x00 52DF
0x00 52E0
0x00 52E1
0x00 52E2
0x00 52E3
0x00 52E4
0x00 52E5
0x00 52E6
0x00 52E7
0x00 52E8
0x00 52E9
0x00 52EA
to
0x00 52FE
0x00 52FF
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530A
0x00 530B
0x00 530C
0x00 530D
0x00 530E
0x00 530F
Table 9. General hardware register map (continued)
Block
Register label
Register name
TIM1
TIM1_DCR2
TIM1_DMA1R
TIM1 DMA1 control register 2
TIM1 DMA1 address for burst mode
Reset status
0x00
0x00
Reserved area (12 byte)
TIM4
TIM4_CR1
TIM4_CR2
TIM4_SMCR
TIM4_DER
TIM4_IER
TIM4_SR1
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 control register 1
TIM4 control register 2
TIM4 Slave mode control register
TIM4 DMA1 request enable register
TIM4 Interrupt enable register
TIM4 status register 1
TIM4 Event generation register
TIM4 counter
TIM4 prescaler register
TIM4 Auto-reload register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reserved area (21 byte)
IRTIM
TIM5
IR_CR
TIM5_CR1
TIM5_CR2
TIM5_SMCR
TIM5_ETR
TIM5_DER
TIM5_IER
TIM5_SR1
TIM5_SR2
TIM5_EGR
TIM5_CCMR1
TIM5_CCMR2
TIM5_CCER1
TIM5_CNTRH
TIM5_CNTRL
TIM5_PSCR
TIM5_ARRH
Infrared control register
TIM5 control register 1
TIM5 control register 2
TIM5 Slave mode control register
TIM5 external trigger register
TIM5 DMA1 request enable register
TIM5 interrupt enable register
TIM5 status register 1
TIM5 status register 2
TIM5 event generation register
TIM5 Capture/Compare mode register 1
TIM5 Capture/Compare mode register 2
TIM5 Capture/Compare enable register 1
TIM5 counter high
TIM5 counter low
TIM5 prescaler register
TIM5 Auto-reload register high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
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DocID17943 Rev 10