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STM8L151X6 Datasheet, PDF (113/146 Pages) STMicroelectronics – Operating conditions
STM8L151x6/8 STM8L152x6/8
Electrical parameters
9.3.13
12-bit DAC characteristics
In the following table, data are guaranteed by design.
Table 50. DAC characteristics
Symbol
Parameter
Conditions
Min. Typ.
VDDA Analog supply voltage
-
1.8
-
VREF+ Reference supply voltage
-
1.8
-
IVREF
Current consumption on VREF+
supply
VREF+ = 3.3 V, no load,
middle code (0x800)
VREF+ = 3.3 V, no load,
worst code (0x000)
-
-
130
220
IVDDA
Current consumption on VDDA
supply
VDDA = 3.3 V, no load,
middle code (0x800)
VDDA = 3.3 V, no load,
worst code (0x000)
-
-
210
320
TA
RL(1) (2)
RO
CL(3)
Temperature range
Resistive load
Output impedance
Capacitive load
DAC_OUT
(4)
DAC_OUT voltage
-40
-
DACOUT buffer ON
5
-
DACOUT buffer OFF
-
8
-
-
DACOUT buffer ON 0.2
-
DACOUT buffer OFF
0
-
Settling time (full scale: for a 12-
bit input code transition between
tsettling the lowest and the highest input RL ≥ 5 kΩ, CL≤ 50 pF
-
7
codes when DAC_OUT reaches
the final value ±1LSB)
Max frequency for a correct
Update rate
DAC_OUT (@95%) change
when small variation of the input
RL ≥ 5 kΩ, CL ≤50 pF
-
-
code (from code i to i+1LSB).
Wakeup time from OFF state.
tWAKEUP Input code between lowest and RL ≥ 5 kΩ, CL≤50 pF
-
9
highest possible codes.
PSRR+
Power supply rejection ratio (to
VDDA) (static DC measurement)
RL≥ 5 kΩ, CL≤50 pF
-
-60
1. Resistive load between DACOUT and GNDA
2. Output on PF0 or PF1
3. Capacitive load at DACOUT pin
4. It gives the output excursion of the DAC
Max.
3.6
VDDA
220
Unit
V
350
µA
320
520
125
°C
-
kΩ
10
kΩ
50
pF
VDDA - 0.2
V
VREF+ -1 LSB V
12
µs
1
Msps
15
µs
-35
dB
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